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E2F0020-18-X2
Semiconductor MSM7662
Semiconductor NTSC/PAL Digital Video Decoder
This version: Oct. 1998 MSM7662
Pr el im in ar y
GENERAL DESCRIPTION
The MSM7662 is an LSI device that decodes NTSC or PAL analog video signals into YCbCr and RGB digital data based on ITU-RBT.601. The device has built-in two channels of A/D converters and can accept composite video and S video signals for the input video signals. Composite video signals are converted to YCbCr and RGB digital data via the 2-dimensional Y/C separation circuit with an adaptive filter. Analog video signals can be sampled by a clock at the pixel frequency or at twice the pixel frequency. A decimation filter is built-in for sampling at twice the pixel frequency. Input signals are synchronized internally and high-speed locking for color burst is possible. Because a FIFO buffer is built into the output format circuit, jitter-free output can be obtained even for non-standard signals.
FEATURES (* new feature not found on MSM7661)
NTSC/PAL composite video signal or S-video signal * 5 composite, 2 S-video analog inputs (switchable) * Built-in clamp circuits and video amps * Built-in 8-bit A/D converters (2 channels; sampling frequency: 40 MHz) * 4 selectable output interfaces ITU-RBT.656 (conditional), 8-bit (YCbCr), 8-bit (Y) + 8-bit (CbCr) YCbCr = 4 : 2 : 2, YCbCr = 4 : 1 : 1 (limit) 24-bit RGB RGB = 4 : 4 : 4 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S-video signal input) NTSC format: 3 lines or 2 lines, PAL format: 2 lines (3 virtual lines) * Selectable input signal synchronization 4 synchronization modes: FIFO-1, FIFO-2, FM-1, FM-2 (FIFO-1 is normally selected) (FIFO-1 and FIFO-2 use the internal FIFO, FM-1 and FM-2 use external field memory) Compatible pixel frequencies 13.5 MHz (ITU-RBT.601), 12.27 MHz (NTSC Square Pixel) 14.31818 MHz (NTSC 4fsc), 14.45 MHz (PAL Square Pixel) * Built-in AGC/ACC circuits, compatible with a wide range of input levels Input level range: -8 dB to +3.5 dB Switchable between AGC/MGC (fixed gain) and ACC/MCC (fixed gain) Decimation filter built into input stage, allows easy configuration of filter prior to A/D converter Automatic NTSC/PAL recognition (only for ITU-RBT.601) Sleep mode Multiplex signal recognition (closed caption) During vertical blanking interval, data is output as 8-bit data. I2C-bus interface 3.3 V single power supply (I/O 5 V tolerance) * Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7662TB) 1/47
Input analog signal
BLOCK DIAGRAM
Semiconductor
CLKX2O INS[2:0] GAINS[2:0] CLKXO
CLKX2 CLKSEL
PLLSEL
VSYNC_L HVALID
VVALID
STATUS1
STATUS3
HSYNC_L
ODD/EVEN
STATUS2
Synchronization Block VRT2 VIN6 VIN5 ADIN2 AMPOUT2 CLPOUT2 VRB2 AGC& AMP
Decimation Filter
M[7:0]
SW
C ADC
Prologue Block
Luminance Block (AGC or MGC + LPF) Epilogue Block ITU-656 & 8 bits (YCbCr) Y[7:0] (G[7:0])
(2 Dim. Y/C separate)
Decimation Filter
VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 VIN4 VIN3 VIN2 VIN1 VRT1
Y ADC
Line Memory (1 Kbyte) 2
Chrominance Block (ACC or MCC + LPF) 8 bits (Y) 8 bits (CbCr)
AGC& AMP
Output Formatter I2C-bus Control Logic Test Control Logic
C[7:0] (R[7:0])
SW Matrix
8 bits (R) 8 bits (G) 8 bits (B)
B[7:0]
MSM7662
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MODE[3:0]
SCL
SDA
RESET_L
SLEEP
SCAN
TEST[2:0]
,
Semiconductor
96 GAINS[0] 95 GAINS[1] 94 GAINS[2] 100 DAGND 99 INS[0] 98 INS[1] 97 INS[2] 92 DGND 93 DVDD
DAVDD VRT2 VIN6 VIN5 1 2 3 4 5 6 7 8 9 ADDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 10 AGND 11 AGND 12 VRB1 13 CLPOUT1 14 AMPOUT1 15 ADIN1 16 VRCL1 17 AGND 18 AVDD 19 VIN4 20 VIN3 21 VIN2 22 VIN1 23 VRT1 24 DAVDD 25
MSM7662
PIN CONFIGURATION (TOP VIEW)
83 STATUS1
82 STATUS2
81 STATUS3
77 CLKX2O
76 CLKXO
75 HSYNC_L 74 VSYNC_L 73 VVALID 72 HVALID 71 ODD/EVEN 70 C[0] 69 C[1] 68 C[2] 67 C[3] 66 C[4] 65 C[5] 64 C[6] 63 C[7] 62 DGND 61 DVDD 60 Y[0] 59 Y[1] 58 Y[2] 57 Y[3] 56 Y[4] 55 Y[5] 54 Y[6] 53 Y[7] 52 DVDD 51 DGND
80 CLKX2 B[4] 46
DAGND 26
MODE[0] 27
MODE[1] 28
MODE[2] 29
MODE[3] 30
SCAN 31
TEST[2] 32
TEST[1] 33
TEST[0] 34
SLEEP 35
RESET_L 36
DVDD 37
DGND 38
SCL 39
SDA 40
PLLSEL 41
CLKSEL 42
B[7] 43
B[6] 44
B[5] 45
B[3] 47
B[2] 48
78 DGND
79 DVDD
91 M[0]
90 M[1]
89 M[2]
88 M[3]
87 M[4]
86 M[5]
85 M[6]
84 M[7]
B[1] 49
100-Pin Plastic TQFP
B[0] 50
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Semiconductor
MSM7662
PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol DAVDD VRT2 VIN6 VIN5 AVDD AGND ADIN2 AMPOUT2 CLPOUT2 VRB2 AGND AGND VRB1 CLPOUT1 AMPOUT1 ADIN1 VRCL1 AGND AVDD VIN4 VIN3 VIN2 VIN1 VRT1 DAVDD DAGND Type -- O I I -- -- I O O O -- -- I O O I I -- -- I I I I O -- -- Description Digital power supply in A/D converter A/D converter reference voltage (high side) for chroma signal Chroma signal input pin (leave open or connect to AGND when not used) Chroma signal input pin (leave open or connect to AGND when not used) Analog power supply Analog ground A/D converter input pin for chroma signal Chroma signal amp output Chroma signal clamp voltage output A/D converter reference voltage (low side) for chroma signal Analog ground Analog ground A/D converter reference voltage (low side) for composite/luminance signal Composite/luminance signal clamp voltage output Composite/luminance signal amp output A/D converter input pin for composite/luminance signal Luminance signal clamp voltate input Analog ground Analog power supply Composite/luminance signal input (leave open or connect to AGND when not used) Composite/luminance signal input (leave open or connect to AGND when not used) Composite/luminance signal input (leave open or connect to AGND when not used) Composite/luminance signal input (leave open or connect to AGND when not used) A/D converter reference voltage (high side) for composite/luminance signal Digital power supply in A/D converter Digital ground in A/D converter Mode selection pins (pulled-down by internal resistors) MODE[3:2] Output mode selection 00: ITU-RBT.656 (with SAV, EAV, blank processing) 01: ITU-RBT.656 (no SAV, EAV, blank processing) 10: ITU-RBT.601 27 to 30 MODE[3:0] I MODE[1] MODE[0] 11: RGB 0: NTSC 0: ITU-RBT.601 1: PAL 1: Square Pixel
If an ITU-R.601 signal is input while registers are set to automatic NSTC/PAL recognition, NTSC/PAL will be automatically recognized regardless of the MODE1 setting.
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Semiconductor
MSM7662
PIN DESCRIPTIONS (continued)
Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 to 50 51 52 53 to 60 61 62 63 to 70 71 72 73 74 75 76 77 78 79 80 Symbol SCAN TEST[2] TEST[1] TEST[0] SLEEP RESET_L DVDD DGND SCL SDA PLLSEL CLKSEL B[7:0] DGND DVDD Y[7:0] DVDD DGND C[7:0] ODD/EVEN HVALID VVALID VSYNC_L HSYNC_L CLKXO CLKX2O DGND DVDD CLKX2 Type I I I I I I -- -- I I/O I I I/O -- -- O -- -- I/O O O O O O O O -- -- I Description Test input. Normally fixed at "0" (pulled down by internal resistor). Test input. Normally fixed at "0" (pulled down by internal resistor). Test input. Normally fixed at "0" (pulled down by internal resistor). Test input. Normally fixed at "0" (pulled down by internal resistor). 0: normal operation, 1: sleep operation Reset input pin (active "L") Digital power supply Digital ground I2C-bus clock input I2C-bus data I/O pin Internal/external sync switching pin (pulled down by internal resistor). 0: Internal sync mode, 1: External sync mode; use external PLL Clock select input pin (pulled down by internal resistor). "L": double-speed 27 MHz, "H": normal clock 13.5 MHz B data output during RGB mode B[7]: MSB, B[0]: LSB Digital ground Digital power supply ITU-RBT.656 data output during ITU-RBT.656 output mode ITU-RBT.601 luminance data output during ITU-RBT.601 output mode G data output during RGB mode, Y[7]: MSB, Y[0]: LSB Digital power supply Digital ground Chroma data output during ITU-RBT.601 output mode R data output during RGB mode, C[7]: MSB, C[0]: LSB Field display output If field is odd, "H" is output Horizontal valid pixel timing output pin Vertical valid line timing output pin V sync output pin H sync output pin Pixel clock output System clock output Digital ground Digital power supply System clock input Default is internal FIFO overflow detection (TV, VTR mode switching guide) 81 STATUS[3] O 0: non-detection, 1: detection CSYNC output (selected by register) When PLLSEL external sync mode is selected, HSYNC output
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Semiconductor
MSM7662
PIN DESCRIPTIONS (continued)
Pin Symbol Type 0: NTSC, 1: PAL HLOCK sync detection display output (selected by register) 0: non-detection, 1: detection 83 84 85 86 87 88 89 STATUS[1] M[7] M[6] M[5] M[4] M[3] M[2] O I/O I/O I/O I/O I/O I/O VBI interval multiplex signal detection output 0: non-detection, 1: detection Field memory control signal; RE output Field memory control signal; WE output Field memory control signal; RSTR output Field memory control signal; RSTW output Test output pin, normally "L" output Slave address select "L": 1000001X "H": 1000011X (no internal pull-up or pull-down resistor) Pin for setting by either external pin or internal register in order to select 90 M[1] I/O analog section gain value and video signal input pin. "L": external pin setting "H": internal register setting (no internal pull-up or pull-down resistor) 91 92 93 94 to 96 97 to 99 100 M[0] DGND DVDD GAINS[2:0] INS[2:0] DAGND I/O -- -- I I -- Test I/O pin, normally fixed at "H" (no internal pull-up or pull-down resistor) Digital ground Digital power supply Inputs for amp gain switch setting during external setting mode (pulled down by internal resistors) Inputs for signal input pin switch setting during external setting (pulled down by internal resistors) Digital ground in A/D converter Description Default is NTSC-PAL recognition 82 STATUS[2] O
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Semiconductor
MSM7662
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Consumption Storage Temperature Symbol VDD VI PW TSTG Condition Ta = 25C VDD = 3.3 V -- -- Rating -0.3 to +4.5 -0.3 to +5.5 1 -55 to +150 Unit V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage Digital "H" Level Input Voltage Digital "L" Level Input Voltage Analog Video Signal Input Operating Temperature Symbol VDD GND VIH1 VIH2 (*1) VIL VAIN Ta Condition Ta = 25C Ta = 25C -- -- -- SYNC tip to white peak level -- Min. 3.0 -- 2.2 0.8 VDD 0 0.8 0 Typ. 3.3 0 -- -- -- -- -- Max. 3.6 -- VDD VDD 0.8 1.1 70 Unit V V V V V VP-P C
*1:
CLKX2, SDA
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Semiconductor
MSM7662
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V) Parameter "H" Level Output Voltage "L" Level Output Voltage Symbol VOH VOL Condition IOH = -4 mA (*1) IOH = -6 mA (*2) IOL= 4 mA (*1) IOL= 6 mA (*2) VI = GND to VDD Input Leakage Current Output Leakage Current SDA Output Voltage SDA Output Current ILI ILO SDAVL SDAIO Rpull_down = 50 kW (*3) VI = GND to VDD -- -- Min. 0.7 VDD 0 -10 -250 -10 0 3 Typ. -- -- -- -- -- -- -- Max. VDD 0.8 +10 -20 +10 0.4 -- Unit V V mA mA mA V mA
*1: *2: *3:
HSYNC_L, VSYNC_L, SYSSEL, C[7:0], B[7:0], ODD, VVALID, HVALID, CLKXO, HSY Y[7:0], CLKX2O MODE[3:0], TE, TEST1, T0, T1, PLLSEL, CLKSEL, M[3:0], ATEST[3:1], INS[3:1]
DC Characteristics (Analog Unit)
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V) Parameter AMPOUT Output Voltage CLPOUT Output Voltage VRT Output Voltage VRB Output Voltage ADIN VIN Input Current Symbol VOAMP VOCLP VRT VRB VIADIN VIVIN IIVIN Condition RO = 330 W RO = 5 kW -- -- -- Capacitive coupling VI = 1.5 V Min. 0.2 0.2 2.05 0.15 VRB 0.4 60 Typ. -- -- 2.3 0.3 -- -- 100 Max. 2.6 1.6 2.4 0.4 VRT 1.3 200 Unit V V V V V VP-P mA
DC Characteristics
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V) Parameter Power Supply Current (Operating) Symbol ID1 Condition AD1 on AD1 off CLKX2 = 27 MHz AD1 on Power Supply Current (Operating) Power Supply Current (Sleep) ID2 IDS AD2 on CLKX2 = 27 MHz VI = 1.5 V 0.2 1 5 mA 190 240 TBD mA 150 210 TBD mA Min. Typ. Max. Unit
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Semiconductor AC Characteristics (Single Speed Mode)
MSM7662
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V) Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Time tCLKX1 NTSC 4fsc NTSC Square Pixel PAL Square Pixel CLKX1 Duty tD_D1 CLKSEL : H Min. -- -- -- -- 40 Typ. Max. 74.07 69.84 81.5 67.8 -- -- -- -- 60 Unit ns ns ns ns %
Output Data Delay Time 1 (*) Output Data Delay Time 2 (*) Output Clock Delay Time (*) (CLKX2-CLKXO) Output Clock Delay Time (*) (CLKX2-CLKX2O) SCL Clock Cycle Time SCL Clock Duty SCL Low Level Cycle (*) Output load: 15 pF
tOD11 tOD12 tCXD11 tCXD12 tC_SC1 tD_SC1 tL_SC1
-- -- CLKSEL : H CLKSEL : H Rpull_up = 4.7 kW -- Rpull_up = 4.7 kW
7 7 3 3 200 -- 100
-- -- -- -- -- 50 --
28 35 22 16 -- -- --
ns ns ns ns ns % ns
AC Characteristics (Double Speed Mode)
(Ta = 0 to 70C, VDD (DVDD, ADVDD, AVDD) = 3.3 V 0.3 V) Parameter Symbol Condition ITU-RS601 CLKX2 Cycle Time tCLKX2 NTSC 4fsc NTSC Square Pixel PAL Square Pixel CLKX2 Duty tD_D2 -- Min. -- -- -- -- 45 Typ. Max. 37.05 34.9 40.75 33.9 -- -- -- -- -- 55 Unit ns ns ns ns %
Output Data Delay Time 1 (*) Output Data Delay Time 2 (*) Output Clock Delay Time (*) (CLKX2-CLKXO) Output Clock Delay Time (*) (CLKX2-CLKX2O) SCL Clock Cycle Time SCL Clock Duty SCL Low Level Cycle (*) Output load: 15 pF
tOD21 tOD22 tCXD21 tCXD22 tC_SCL tD_SCL tL_SCL
CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L Rpull_up = 4.7 kW -- Rpull_up = 4.7 kW
8 8 6 5 200 -- 100
-- -- -- -- -- 50 --
28 34 22 16 -- -- --
ns ns ns ns ns % ns
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Semiconductor
MSM7662
INPUT AND OUTPUT TIMING
Clock and Output Timing
CLKSEL:H tCLKX1 CLKSEL:L tCLKX2
CLKX2 tCXD12 CLKX2O tCXD11 CLKXO tOD11 Y[7:0], C[7:0] HVALID, VVALID, ODD/EVEN, STATUS[3:1], M[7:4], B[7:0] HSYNC_L, VSYNC_L tOD12 tOD22 tOD21 tCXD21 tCXD22
I2C-bus Interface Input/Output Timing The basic input/output timing of the I2C-bus is indicated below.
SDA SCL
MSB
S Start condition
1
2
7
8
9 ACK
1 tC_SCL
2 3-8
9 ACK
P Stop condition
Data line stable: data valid
Change of data allowed
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Semiconductor
MSM7662
FUNCTIONAL DESCRIPTION
Analog Unit 1) Analog input select: Compatible with composite video signals and S-video signals. Input selection can be switched by register control via the I2C-bus or by external pins. (See the below chart for pin combinations.) 2) Clamp function: An analog clamp and a digital pulse clamp can be used. Analog clamp (HSY = 1)* Analog clamp AE HSY clamp (digital clamp) HSY clamp (digital clamp) Only the HSY clamp can be set as the pedestal clamp. 3) AGC amp: The AGC function operates depending upon the input level. Manual gain setting is also possible. This AGC function operates at 2 stages, the analog unit and digital unit. Digital decoded data is output in conformance with ITU-RBT.601. 4) A/D converter: Two internal 8-bit A/D converters sample at twice the pixel frequency. (Sampling at the pixel frequency is possible by changing the register setting.) List of Analog Input Conditions
Input Signal Composite Input* Composite Input Composite Input Composite Input Composite Input S-video Input S-video Input All inputs Off @Control Pin INS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Luminance Luminance OFF (Sleep) VIN1 Composite Composite Composite Composite Composite Chroma Chroma VIN2 Input Pin VIN3 VIN4 VIN5 VIN6 ADC Selection ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF ON ON OFF
Blank spaces: non-selectable *: register default setting after LSI reset @: These pin settings are valid during external mode setting. In the internal register mode, the register contents will be changed. Manual Gain Control (analog AMP gain)
Gain Setting Pins GAINS[2:0] [000] [001] [010] [011] [100] [101] [110] [111] Set Gain Value Typ. Value (multiplication factor) 1.0 1.35 1.75 2.3 3.0 3.8 5.0 2.0
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Semiconductor Decoder Unit 1. Prologue Block
MSM7662
The prologue block inputs data and performs Y/C separation. Data can be input at either the pixel frequency (ITU-R: 13.5 MHz) or at twice the pixel frequency (ITU-R: 27 MHz). If input at twice the pixel frequency, data is processed after passing through a decimator circuit to convert it to the pixel frequency. The decimator circuit may be bypassed by changing the register setting, regardless of whether data is input at the normal pixel frequency or at twice the pixel frequency. If a composite signal (CVBS) is input, the default setting performs Y/C separation using a 2dimensional adaptive comb filter. The following operating modes can be selected via the I2C-bus. Default settings are indicated by an asterisk (*). The default state is selected at reset. 1) Video input mode selection Composite video input * S-video input 2) Video input mode selection NTSC/PAL auto-select* (only for ITU-R.601) Dependent upon operating mode selected When ITU-R.601 is selected, the video input mode is automatically set depending upon the number of lines per field. 3) Operating mode selection NTSC ITU-R.601 13.5 MHz* NTSC Square Pixel 12.27 MHz NTSC 4fsc 14.31818 MHz PAL ITU-R.601 13.5 MHz PAL Square Pixel 14.75 MHz 4) Decimator circuit pass/bypass selection Pass through decimator circuit* Bypass decimator circuit 5) Y/C separation mode selection Use adaptive comb filter* Use non-adaptive comb filter Do not use comb filter (use trap filter) The adaptive comb filter makes the correlation between up to 3 consecutive lines (only 2 lines in the case of a PAL signal). If there is correlation, Y/C separation is performed by the comb filter according to the format of correlation. The non-adaptive comb filter performs Y/C separation by removing the luminance component based on the average of preceding and following lines (when there is correlation between 3 lines). When a comb filter is not used, Y/C separation is performed by a trap filter.
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Semiconductor If an S-video signal is input, these Y/C separation circuits are bypassed.
MSM7662
The functions of this block only operate when lines are valid as image information. During the V blanking interval, CVBS signals are not processed. 2. Luminance Block The luminance block removes synchronous signals from signals containing luminance components after Y/C separation. The signals are compensated and then output as luminance signals. Two modes of gain control functions can be selected for the luminance signal output level: AGC (Auto Gain Control) and MGC + Pedestal Clamp. In the AGC mode, luminance level amplification is determined by comparing the SYNC depth with a reference value. The default is 40IRE and can be changed by the register setting. The input has a sync chip clamp. In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level of the input. Signal amplification and black level can be changed from the clamped position by register settings. This block can select the follwing operating modes. 1) Selection of prefilter and sharp filter usage Do not use* Use These filters are used to enhance the edges of luminance component signals. 2) Selection of aperture bandpass filter coefficient Middle range* High range 3) Coring range selection Off* 4LBS 5LBS 7LBS 4) Aperture weighting coefficient selection 0* 0.25 0.75 1.5 Both coring and aperture compensation processes perform contour compensation. 5) Selection of pixel position compensating circuit usage Use* Do not use 6) AGC loop filter time constant selection Slow coefficient value 1/1024n Medium 1/64n* Fast 1/n Fixed 0 Fixed: manual gain setting is possible
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Semiconductor
MSM7662
7) Parameter for fine adjustment of AGC sync depth 8) Parameter for fine adjustment of sync removal level The black level is adjusted. The default setting outputs the pedestal position as a black level (=16). 9) Pedestal clamp selection Do not use pedestal clamp* Use pedestal clamp (at this time, AGC does not operate, MGC operates) 3. Chrominance Block This block processes the chroma signals. The following operating modes can be selected. 1) Selection of color bandpass filter usage Do not use* Use 2) ACC loop filter time constant selection Slow coefficient value 1/1024m Medium 1/64m* Fast 1/m Fixed 0 Fixed: manual gain setting is possible 3) ACC reference level fine adjustment 4) Parameter for burst level fine adjustment 5) Threshold level at which chroma amplitude becomes valid is selected based upon color burst ratio. 0.5 0.25* 0.125 Off Off: The color killer function is turned off. If decoloration occurs while decoding a still picture, setting the threshold level to "off" will reduce the decoloration. 6) Color killer mode selection Auto color killer mode* Forced color killer 7) Parameter for fine adjustment of color subcarrier phase In this block, chroma signals pass through a bandpass filter to cut out unnecessary band. To maintain a constant chroma level, these signals then pass through an ACC compensating circuit and are UV demodulated. (The filter can be bypassed.) If the demodulated result does not reach a constant level, color killer signals are generated to fix the ACC gain. This functions as an auto color killer control circuit. The UV demodulated results pass through a low-pass filter and are output as chrominance signals.
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Semiconductor 4. Synchronization Block
MSM7662
This block processes the sync signals. Synchronous signals are generated for chip output and for internal use. Various signals are output from this block and the following operating modes can be selected. 1) Adjustment of SYNC threshold level (internal sync) 2) HSY control 2-1) Fine adjustment of HSY signal (start side) 2-2) Fine adjustment of HSY signal (stop side) 3) HSY signal enable selection High Level* Active Low Level The HSY signal provides the sync-tip-clamp processing for the A/D converter. 4) Fine adjustment of HSYNC_L signal 5) HVALID control 5-1) Fine adjustment of HVALID signal (start side) 5-2) Fine adjustment of HVALID signal (stop side) 6) VVALID control 6-1) Fine adjustment of VVALID signal (start side) 6-2) Fine adjustment of VVALID signal (stop side) Data signals are transferred at the rising edge of the HVALID signal. 7) FIFO and Field Memory mode selection FIFO-1 mode*: Sets and outputs a standard value for the number of pixels per 1H from the internal FIFO. This mode is also compatible (to a degree) with non-standard VTR signals. FIFO-2 mode: Sets and outputs a constant pixel number corresponding to the input H interval for the number of pixels per 1H from the internal FIFO. FM-1 mode: This mode outputs the decoded results according to the SYNC signal. Usage of external field memory is required to manage the number of pixels and to absorb jitter. Memory control signals are to be generated externally. FM-2 mode: This mode is compatible with considerably distorted non-standard VTR signals. Jitter is absorbed by using external field memory (2 Mb 2) and the standard value is set as the pixel number. Field memory control signals are output simultaneously from M[7:4]. 8) Field memory control signals If the FM-1 mode uses external field memory (2 Mb 2) instead of the internal FIFO, field memory control signals are supplied from pins M[7:4].
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Semiconductor 5. Epilogue Block
MSM7662
The Epilogue Block outputs the UV signal from the Chrominance block and the Y signal from the Luminance block in a format based on a signal obtained from the control register setting. This block can select the following modes. 1) Output mode selection 1-1) ITU-RBT.656 (SAV, EAV, blank processing) 1-2) * 8-bit (YCbCr) output (2x pixel clock) synchronization with HSYNC_L, VSYNC_L 1-3) 16-bit (8-bit Y/8-bit CbCr) (pixel clock) synchronization with HSYNC_L, VSYNC_L 1-4) 24-bit RGB (8 bits each) synchronization with HSYNC_L, VSYNC_L 2) Enable Blue Back display when synchronization fails OFF ON* 3) Selection of YCbCr signal output format YCbCr 4 : 2 : 2* YCbCr 4:1:1 The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an output format to be described later. 4) Selection of 8-bit chroma signal output format Offset binary* 2's complement 5) Output pin enable selection High-impedance Output enable* 6) Multiplex signal (VBI data) detection level adjustment The levels to detect multiplexed signals sent during the vertical blanking period are configured to be variable. The binary values after input signals are A-to D converted are employed as the levels to detect multiplexed signals, and the levels are set in eight steps with respect to the SYNC tip level. (See page 26 and page 27) 7) Various mode detection NTSC/PAL detection Multiplex signal detection HSYNC synchronization detection Iunternal FIFO overflow detection 8) Output signal phase control Y and C phases can each be adjusted in the range of -2 to +1 pixels. 6. I2C Control Block This serial interface block is based on the I2C standard of the Phillips Corporation. This block only functions as a Slave-Receiver (write mode). 7. Test Control Block This block is used to test the LSI chip. Normally this block is not used.
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Semiconductor Input Signal Level
MSM7662
The figure below shows the ideal range of the input signal, considered as an 8-bit straight binary value.
255 reserved 200 246
Iuminance
chrominance +DC
NTSC:60 (PAL:63) sync 4 0
input black level 13 input sync-tip level NTSC/PAL: CVBS[7:0] input range
The above input conditions are ideal. Because analog signals are normally input at different levels, the exact settings described above are difficult to achieve. While maintaining the ratio of White Peak (100%)/SYNC = 100IRE/40IRE (NTSC), if the input signal is set within the A/D converter's voltage range, the Y digital output will be output with Black Level = 16 and White Peak (100%) = 235.
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Semiconductor Output format
MSM7662
ITU-RBT.656 output, 8-bit (YCbCr) output, and 16-bit (8-bit Y/8-bit CbCr) output have the following formats. The YCbCr 4:2:2 format and 4:1:1 format are shown below. The output format can be changed by register settings.
Output Y7 (MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0 (LSB) C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) Y point C point Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 0 0 Pixel Byte Sequence Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 2 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 4 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 5 Output Y7 (MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0 (LSB) C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) Y point C point Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 1 0 YCbCr 4:1:1 format Pixel Byte Sequence Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 5 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 6 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 7
YCbCr 4:2:2 format
Relation between video mode and pixel number (default settings when standard signal is input)
Video Mode NTSC Pixel Type ITUR.601 Square pixel 4fsc PAL ITUR.601 Square pixel Pixel Rate (MHz) 13.5 12.27 14.32818 13.5 14.75 Total Pixels 858 780 910 864 944 Active Pixels 720 640 768 720 768 FrontPorch 16 28 8 12 34 Hsyc BackPorch 122 112 134 132 142 HBLK Total 138 140 142 144 176
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Semiconductor
MSM7662
TIMING DESCRIPTION
Vertical Synchronizing Signal The vertical synchronizing signal timing is as follows.
524 CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD 262 CVBS HVALID HSYNC_L VSYNC_L CSYNC_L VVALID ODD
525
1
2
3
4
5
6
7
8
9
21
22
263
264
265
266
267
268
269
270
271
283
284
285
Vertical Synchronizing Signal (60 Hz)
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Semiconductor
MSM7662
621 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD 309 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD
622
623
624
625
1
2
3
4
5
6
23
24
310
311
312
313
314
315
316
317
318
336
337
338
Vertical Synchronizing Signal (50 Hz)
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Semiconductor A/D Converter Support Signal
MSM7662
The waveform of the HSY signal, shown below, provides clamp timing to the A/D converter when HSY clamp (digital clamp) is selected. The start and end edges of the clamp pulse have a variable range from the sync chip to the pedestal position.
CVBS BURST
COLOR BURST
HSY
A/D Converter Support Signal Output Timing * ITU-R.656 output
T : clock periods 37 ns normal (1/27 MHz) SAV : start of active video timing reference code EAV : end of active video timing reference code Digital line {1716T (NTSC, 525), 1728T (PAL, 625)} Multiplexed video data Cb0 Y00 Cr0 Cb1 Y10 Cr1 Y11 4T Digital active line Video data block (1440T)
SAV
ITU-R BT.656 Output (Data in one line in which video data presents) During the blanking interval, data is output with the Y value. Note: Digital line 1716T (NTSC, 525) and 1728T (PAL, 625) are not maintained at the next line. Digital active line 1440T of the line immediately after VVALID falls and the 10th or 11th line after VSYNC_L rises will fluctuate due to pixel compensation. Especially when a non-standard signal is input, the line immediately after VVALID falls will fluctuate largely due to instability of the input signal. Due to phenomena such as an increase in the number of lines for a standard signal and a decrease in the number of lines for a nonstandard signal, it may not be possible to guarantee correct EAV and SAV functionality. 21/47
EAV
4T Digital line blanking 276T (NTSC, 525) 288T (PAL, 625)
EAV
Semiconductor Contents of SAV and EAV Both SAV and EAV consist of 4 words. Their configuration is shown below.
Word First Second Third Fourth Bit No. 7 (MSB) 1 0 0 1 6 1 0 0 F 5 1 0 0 V 4 1 0 0 H 3 1 0 0 P3 2 1 0 0 P2 1 1 0 0 P1 0 (LSB) 1 0 0 P0
MSM7662
F = 0: during field 1 1: during field 2 V = 0: elsewhere 1: during field blanking H = 0: SAV H = 1: EAV P3, P2, P1, P0: Protection bit
The 4th word of SAV and EAV The relationship between the F, V, H and Protection bits in the 4th word of SAV and EAV is shown below.
Bit No. Function 0 1 2 3 4 5 6 7 7 (MSB) Fixed 1 1 1 1 1 1 1 1 1 6 F 0 0 0 0 1 1 1 1 5 V 0 0 1 1 0 0 1 1 4 H 0 1 0 1 0 1 0 1 3 P3 0 1 1 0 0 1 1 0 2 P2 0 1 0 1 1 0 1 0 1 P1 0 0 1 1 1 1 0 0 0 P0 0 1 1 0 1 0 0 1
Usually, V = 1 during blanking, however when VBI data is detected and V = 0 is the desired output, set the MRC[3] SAV, EAV V-status of Mode Register C (MRC) to "1".
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Semiconductor
MSM7662
CLKX2 HVALID Y[7:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4
Cr n-4 Y n-3 Cb n-2 Y n-2 Cr n-2 Y n-1
8-bit (YCbCr: 2x clock) Output
CLKX2 CLKO HVALID Y[7:0] C(7:0) Y0 Cb0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y(n-2) Y(n-1)
Cb(n-2) Cr(n-2)
16-bit (Y: 8-bit, CbCr: 8-bit) Output
CLKX2 CLKO HVALID R[7:0] G[7:0] B[7:0] R0 G0 B0 R1 G1 B1 R2 Cb2 B2 R3 Cr3 B3 R(n-2) G(n-2) B(n-2) R(n-1) G(n-1) B(n-1)
24-bit (R: 8-bit, G: 8-bit, B: 8-bit) Output 23/47
Semiconductor
MSM7662
* Timing when using external field memory Field memory timing in the FM-2 mode, using control signals from the decoder Field memory: MSM518222, 2 units are used (Y and C) Four memory control signals are supplied from the decoder, M[4]: RSTW, M[5]: RSTR, M[6]: WE:, and M[7]: RE. NTSC Signal (13.5 MHz)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR RE Y (7:0) C (7:0)
NTSC: ODD Field
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR RE Y (7:0) C (7:0)
NTSC: EVEN Field 24/47
Semiconductor PAL Signal (13.5 MHz)
MSM7662
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 39 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR RE Y (7:0) C (7:0)
PAL: ODD Field
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 31 32 33 34 35 36 37 38 hsync_l vsync_l hvalid vvalid odd-even y (7:0) c (7:0) RSTW WE HSYNC_L VSYNC_L HVLID VVALID ODD/EVEN RSTR RE Y (7:0) C (7:0)
PAL: EVEN Field
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Semiconductor Horizontal Synchronization Signal The horizontal synchronization signal timing is shown below.
MSM7662
Y[7:0]
HVALID HSYNC_L 60 pixels
Horizontal Timing VBI Data Detection (when a Composite signal is input): STATUS1 Timing VBI data detection results are output from the STATUS1 pin.
Detection level OMR[5:3] 80 to 136 video in
STATUS1 HVALID
HSYNC_L
Y[7:0]
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Semiconductor VBI Data Detection (when an S-Video signal is input): STATUS1 Timing VBI data detection results are output from the STATUS1 pin.
Detection level OMR[5:3] 80 to 136 video in
MSM7662
STATUS1 HVALID
HSYNC_L
Y[7:0]
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Semiconductor I2C-bus Interface Input and Output Timing Basic input and output timing of the I2C-bus interface is shown below.
MSM7662
SDA SCL
MSB
S Start Condition
1
2
7
8
9 ACK
1 tC_SCL
2 3-8
9 ACK
P Stop Condition
Data Line Stable: Data Valid Change of Data Allowed
I2C-bus Basic Input/Output Timing
I2C BUS FORMAT
The I2C-bus interface input format is shown below.
S Slave Address Symbol S Slave Address A Subaddress Data n P Start condition Slave address 1000001X, 8th bit is write signal ["0"] or read signal ["1"] Acknowledge. Generated by slave Subaddress byte Data to write to address designated by subaddress. Stop condition A Subaddress A Data 0 A ...... Data n A P
Description
As mentioned above, the write operation can be executed from subaddress to subaddress continuously. When the write operation is executed at subaddresses discontinuously, the Acknowledge and Stop condition formats are input repeatedly after Data 0. If one of the following matters occurs, the decoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The write attribute of a register does not match "X" (read ["1"]/write ["0"] control bit). The input timing is shown below.
SDA SCL
1
2
8
ACK
1
2
8
ACK
1
2
8
ACK
S Start Condition
Slave Address
Sub Address
Data Stop Condition
P
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Semiconductor
MSM7662
OPERATING MODE SETTING
There are two types of video mode settings. 1. External pin mode: direct setting from dedicated pins 2. Register setting mode: specification by internal register settings These modes can be switched by the mode register MRA[0]. The reset state (default) is the external pin mode. The following registers can be set in the external pin mode. MRA[3:1] Input signal mode *000: NTSC ITU-RBT.601 13.5 MHz 001: NTSC Square Pixel 12.27 MHz 010: NTSC 4fsc 14.31818 MHz 100: PAL ITU-RBT.601 13.5 MHz 101: PAL Square Pixel 14.75 MHz 00: ITU-R BT.656 (SAV, EAV, blank processing) *01: 8 bit (Y CbCr) HSYNC_L and VSYNC_L used for synchronization 10: ITU-R BT.601 16 bit (8 bit Y, 8 bit CbCr) 11: RGB (8 bit R, 8 bit G, 8 bit B)
MRA[7:6]
Output mode
Note:
NTSC 4fsc cannot be set externally.
Pin Setting Example NTSC, 27 MHz (ITU-RBT.601), Composite input, 8-bit (YCbCr) Output
Pin name MODE[3] MODE[2] MODE[1] MODE[0] CLKSEL PLLSEL INS[2:0] GAINS[2:0] TEST[2:0] SCAN M[2] M[1] M[0] SLEEP = low = high = low = low = low = low = low = low = low = low = = low = low = : low = 1000001, : high = 1000011 Normally set to a low level 0 : normal operation 1 : sleep operation Normally set to a low level Condition 10 : 16-bit (Y + CbCr) 0 : NTSC 1 : PAL 1 : Square Pixel 1 : pixel frequency 0 : ITU-RBT.601 Notes 0 : ITU-RBT.656 01 : 8-bit (YCbCr) 11 : RGB
0 : twice the pixel frequency
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Semiconductor
MSM7662
INTERNAL REGISTERS
Register List
Register Function Mode Register A (MRA) Mode Register B (MRB) Mode Register C (MRC) Horizontal Sync Trimmer (HSYT) Sync Threshold level adjust (STHR) Horizontal Sync Delay (HSDL) Horizontal Valid Trimmer (HVALT) Vertical Valid Trimmer (VVALT) Luminance Control (LUMC)
AGC/Pedestal Loop filter Control (AGCLF)
Write Sub/Read address Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Read 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 20
Data byte D7 MRA7 MRB7 MRC7 HSYT7 STHR7 HSDL7 D6 MRA6 MRB6 MRC6 HSYT6 STHR6 HSDL6 D5 MRA5 MRB5 MRC5 HSYT5 STHR5 HSDL5 D4 MRA4 MRB4 MRC4 HSYT4 STHR4 HSDL4 D3 MRA3 MRB3 MRC3 HSYT3 STHR3 HSDL3 D2 MRA2 MRB2 MRC2 HSYT2 STHR2 HSDL2 D1 MRA1 MRB1 MRC1 HSYT1 STHR1 HSDL1 D0 MRA0 MRB0 MRC0 HSYT0 STHR0 HSDL0
HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0 VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0 LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0 AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0 SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0 CHRC7 HUE7 OPCY7 OPCC7 OMR7 ADC17 ADC27 ADC37 ZLD7 CHRC6 HUE6 OPCY6 OPCC6 OMR6 ADC16 ADC26 ADC36 ZLD6 CHRC5 HUE5 OPCY5 OPCC5 OMR5 ADC15 ADC25 ADC35 ZLD5 CHRC4 HUE4 OPCY4 OPCC4 OMR4 ADC14 ADC24 ADC34 ZLD4 CHRC3 HUE3 OPCY3 OPCC3 OMR3 ADC13 ADC23 ADC33 ZLD3 CHRC2 HUE2 OPCY2 OPCC2 OMR2 ADC12 ADC22 ADC32 ZLD2 CHRC1 HUE1 OPCY1 OPCC1 OMR1 ADC11 ADC21 ADC31 ZLD1 CHRC0 HUE0 OPCY0 OPCC0 OMR0 ADC10 ADC20 ADC30 ZLD0 ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0
Sync separation level (SSEPL) Chrominance Control (CHRC) ACC Loop filter Control (ACCLF) Hue Control (HUE)
Output phase Control for Data Y (OPCY) Output phase Control for Data C (OPCC)
Optional Mode Register (OMR)
ADC register (ADC1) ADC register (ADC2) ADC register (ADC3) 0 level detect register (ZLD) Stataus register (STATUS)
STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0
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Semiconductor
MSM7662
Register Parameters
Registers controlled from the I2C-bus are listed below. An asterisk (*) indicates that the register setting value is the default value. Mode Register A (MRA) MRA[7:6] Write only 00: ITU-R BT.656 (SAV, EAV, blank processing) *01: Y,C 8 bits (SAV, EAV, without blank processing) 10: Y,C 16 bits 11: RGB 24 bits *0: Offset binary 1: 2's Complement *0: Composite video input 1: S-video input *000: NTSC ITU-R BT.601 13.5 MHz 001: NTSC Square Pixel 12.27 MHz 010: NTSC 4fsc 14.31818 MHz 100: PAL ITU-R BT.601 13.5 MHz 101: PAL Square Pixel 14.75 MHz *0: External pin mode 1: Register mode *00: FIFO-1 (use internal memory) 01: FIFO-2 (use internal memory) 10: FM-1 (use external memory, external control) 11: FM-2 (use external memory, control signals supplied from M[7:4]) *0: Auto color killer (Chrominance signal level is set to "0" if the color burst level is below the specified value.) *1: Forced color killer (Chrominance signal level is forced to "0".) 0: OFF (Video signal is demodulated and output regardless of synchronization detection.) *1: AUTO (Blue Back is output when synchronization is not detected.) *00: Analog Clamp (HSY = 1) 01: Analog, HSY hybrid clamp 10: HSY clamp 11: HSY = 0 *00: Adaptive comb filter (Correlation of 3 lines is monitored and operating mode is selected.) 01: Non-adaptive comb filter (Operating mode is always fixed.) 10: Use trap filter. (Comb filter is not used.) 11: Undefined
Video output mode
MRA[5] MRA[4] MRA[3:1]
Chroma format Video input model Video Input mode2
MRA[0]
Disable MODE[3:0] pin
Mode Register B (MRB) MRB[7:6]
Write only
Synchronization mode
MRB[5]
Color killer mode
MRB[4]
Blue Back
MRB[3:2]
Clamp mode
MRB[1:0]
Y/C separation mode
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Semiconductor Note: Adaptive comb filter Non-adaptive comb filter 2/3-line comb filter for NTSC Comb filter/trap filter for PAL 3-line comb filter for NTSC 2-line cosine comb filter for PAL
MSM7662
Mode Register C (MRC) MRC[7]
Write only
0: Fix *1: Auto MRC[6] Sub Pixel Alignment *0: Use pixel position compensating circuit. 1: Do not use pixel position compensating circuit. MRC[5] Pixel Sampling Rate *0: (4:2:2) 1: (4:1:1) MRC[4] Data-pass control *0: Use DECIMATOR at 2x sampling 1: Do not use DECIMATOR Note: This register is valid when a 2x clock (27 MHz) is input. MRC[3] SAV, EAV V-status *0: During blanking, V = 1 1: During blanking, while VBI data is not detected, V = 1 MRC[2] RGB output level *0: 0 to 255 1: 16 to 235 MRC[1:0] Undefined Set to 0 Horizontal Sync Trimmer (HSYT) HSYT[7:4] HSYT[3:0] Write only $C to $B (*$0): -4 to +11 (-32 to +88 pixels) $C to $B (*$0): -4 to +11 (-32 to +88 pixels) $00 to $FF (*$1E): 0 to 255
NTSC/PAL Auto select
HSY start trimmer ( 8 pixels) HSY stop trimmer ( 8 pixels) Write only
Sync. Threshold level adjust (STHR) STHR[7:0] Sync. depth
Horizontal Sync Delay (HSDL) HSDL[7:0]
Write only

HSYNC_L delay trimmer ( 1 pixel) $80 to $7F (*$00): -128 to +127 (-128 to +127 pixels) Note: In the internal sync separation (PLLSEL: Low) mode, the HSYNC_L sync signal output position is adjusted. In the external sync separation (PLLSEL: High) mode, the phase shift of the H-Sync input and video signal input is adjusted. Horizontal Valid Trimmer (HVALT) Write only
HVALT[7:4] HVALID start trimmer ( 2 pixels) $8 to $7 (*$0): -8 to +7 (-16 to +14 pixels) HVALT[3:0] HVALID stop trimmer ( 2 pixels) $8 to $7 (*$0): -8 to +7 (-16 to +14 pixels)
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Semiconductor Vertical Valid Trimmer (VVALT) Write only $8 to $7 (*$0): -8 to +7 $8 to $7 (*$0): -8 to +7
MSM7662
VVALT[7:4] VVALID start trimmer ( 1 line) VVALT[3:0] VVALID stop trimmer ( 1 line) Luminance Control (LUMC) LUMC[7] Write only
*0: OFF 1: ON Note: Control range while limiter is ON: 16...235 LUMC[6] Use of Pre-filter *0: Do not use prefilter 1: Use prefilter LUMC[5:4] Aperture bandpass select *00: range0 (middle) 01: range1 10: range2 11: range3 (high) LUMC[3:2] Coring range select *00: coring off 01: +/-4LSB 10: +/-5LSB 11: +/-7LSB LUMC[1:0] Aperture filter weighting factor *00: 0.00 01: 0.25 10: 0.75 11: 1.50 AGC/Pedestral Loop filter control (AGCLF) Write only
Output level limiter

AGCLF[7:6] AGC loop filter time constant 00: slow *01: medium 10: fast 11: MGC mode AGCLF[5:0] AGC reference level $20 to $1F (*$00): -32 to +31 Sync separation level (SSEPL) Write only SSEPL[7] SSEPL[6:0] Pedestal Clamp on/off Sync. separation level *0: Do not use pedestal clamp 1: Use pedestal clamp (AGC stops operating) $40 to $3F (*$00): -64 to +63
Chrominance Control (CHRC) Write only CHRC[7:4] CHRC[3] Set 0 *0: OFF 1: ON Note: Control range while limiter is ON: 16...224 Undefined C-Output level limiter
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Semiconductor CHRC[2] CHRC[1:0] Chroma bandpass filter Color kill threshold factor 0: OFF *1: ON 00: 0.500 color burst level *01: 0.250 color burst level 10: 0.125 color burst level 11: Color killer off
MSM7662
ACC Loop filter control (ACCLF) Write only

ACCLF[7] Undefined Set 0 ACCLF[6:5] ACC loop filter time constant 00: slow *01: medium 10: fast 11: MCC mode ACCLF[4:0] ACC reference level $10 to $0F (*$00): -16 to +15
Hue control (HUE) HUE[7:0] Hue control
Write only
$80 to $7F (*$00): -180 to +178.6 degrees
Output phase control for data Y (OPCY) Write only OPCY[7:2] OPCY[1:0]

Undefined Set 0 Output phase control for data Y *00: normal 01: forward l clock 10: backward 2 clock 11: backward l clock
Output phase control for data C (OPCC) Write only OPCC[7:2] OPCC[1:0]

Undefined Set 0 Output phase control for data C *00: normal 01: forward l clock 10: backward 2 clock 11: backward l clock
Optional Mode Register (OMR) Write only OMR[7] HSY output timing select *0: Use A/D clamp position adjust circuit 1: Do not use A/D clamp position adjust circuit 34/47
Semiconductor OMR[6]
MSM7662
OMR[5:3]
OMR[2]
OMR[1] OMR[0]
VSYNC output timing select *0: VSYNC_L is synchronized to HSYNC_L and then output 1: VSYNC_L is output when a VSYNC input signal is detected. Multiplex signal detection level (VBID etc.) 000: 80 001: 88 *010: 96 011: 104 100: 112 101: 120 110: 128 111: 136 Hi-Z Output in SLEE MODE *0: Active 1: Hi-Z Status2 output mode *0: NTSC/PAL identification 1: HLOCK sync detection Status3 output mode *0: TV/VCR identification 1: CSYNC Write only *0: Use 1: Do not use *0: Use 1: Do not use *00: 1.0 01: 1.5 10: Undifined 11: 2.0 *000: ADI-VIN1 (composite) 001: ADI-VIN2 (composite) 010: ADI-VIN3 (composite) 011: ADI-VIN4 (composite) 100: ADI-VIN5 (composite) 101: ADI-VIN1 (Y), AD2-VIN5 (C) 110: ADI-VIN2 (Y), AD2-VIN6 (C) 111: Prohibited setting (ADC enters sleep state)
ADC register 1 (ADC1) ADC1[7] ADC1[6] ADC1[5:4]
Video amp select Comparator select Clamp current select
ADC1[2:0]
ADC input select
ADC register 2 (ADC2) ADC2[7]
Write only
ADC gain control mode select 0: manual *1: auto 000: 1.00 *001: 1.35 010: 1.75 011: 2.30 100: 3.00 35/47
ADC2[6:4]
ADC gain manual select
Semiconductor 101: 3.80 110: 5.00 111: 2.05 ADC initialize condition gain select 0: not initialize *1: initialize ADC gain control and stage select 00: 2nd change end 01: 3rd change end *10: 3rd change loop Write only
MSM7662
ADC2[3]
ADC2[1:0]
ADC register 3 (ADC3) ADC3[7] ADC3[6:4]
ADC3[2:0]
Undefined Set 0 ADC gain control margin level select 000: 10 mV 001: 20 mV *010: 40 mV 011: 80 mV 100: 160 mV ADC gain control line select 000: 1 line 001: 2 lines *010: 4 lines 011: 8 lines 100: 16 lines Write only
0 level detect register (ZLD) ZLD[7:3] ZLD[2:0]
Undefined Set 0 0 level detect width ( 8 pixel) 000: Undefined 001: 8 pixels *010: 16 pixels 011: 24 pixels 100: 32 pixels 101: 40 pixels 110: 48 pixels 111: 56 pixels Read only
Status register (STATUS) STATUS[7:5] STATUS[4] STATUS[3] STATUS[2] STATUS[1] STATUS[0]
Undefined VBI interval multiplex signal detection 0: Non-detection, 1: Detection HLOCK sync detection 0: Non-detection, 1: Detection NTSC/PAL identification 0: NTSC, 1: PAL TV1/TV2 identification Mode Register B (bit 6) 0: TV1, 1: TV2 FTFO overflow detection 0: Non-detection, 1: Detection 36/47
Semiconductor Relationship between Register Setting Value and Adjusted Value Horizontal Sync Trimmer Position adjustment of sync chip clamp timing signal HSYT [7:4] :Adjusting the starting position
D E F 0 0 1 2 3 4 5 6 7 8 9 A
MSM7662
Register Setting Value (Ox) C
B
Adjusted Value (Pixel) -32 -24 -16 -8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
HSYT [3:0]
:Adjusting the end position
D E F 0 0 1 2 3 4 5 6 7 8 9 A B
Register Setting Value (Ox) C
Adjusted Value (Pixel) -32 -24 -16 -8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
Horizontal Sync Delay Adjustment of the starting position of horizontal sync signal HSDL [7:0]
MSB[7 : 4] 8 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F 9 A B -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 -69 -68 -67 -66 -65 C -64 -63 -62 -61 -60 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 D -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 E -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 F -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 3 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 4 +64 +65 +66 +67 +68 +69 +70 +71 +72 +73 +74 +75 +76 +77 +78 +79 5 +80 +81 +82 +83 6 7 -128 -112 -96 -127 -111 -95 -126 -110 -94 -125 -109 -93 -124 -108 -92 -123 -107 -91 -122 -106 -90 -121 -105 -89 -120 -104 -88 -119 -103 -87 -118 -102 -86 -117 -101 -85 -116 -100 -84 -115 -99 -114 -98 -113 -97 -83 -82 -81 +96 +112 +97 +113 +98 +114 +99 +115
+84 +100 +116 +85 +101 +117 +86 +102 +118 +87 +103 +119 +88 +104 +120 +89 +105 +121 +90 +106 +122 +91 +107 +123 +92 +108 +124 +93 +109 +125 +94 +110 +126 +95 +111 +127
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Semiconductor Horizontal Valid Trimmer Position adjustment of horizontal valid pixel timing signal HVALT [7:4]
Register Setting Value (Ox)
MSM7662
:Adjusting the starting position
8 9 A B C D -6 E -2 F -1 0 0 1 +2 2 +4 3 +6 4 5 6 7 +8 +10 +12 +14
Adjusted Value (Pixel) -16 -14 -12 -10 -8
HVALT [3:0]
Register Setting Value (Ox)
:Adjusting the end position
8 9 A B C D -6 E -4 F -2 0 0 1 +2 2 +4 3 +6 4 5 6 7 +8 +10 +12 +14
Adjusted Value (Pixel) -16 -14 -12 -10 -8
Vertical Valid Trimmer Position adjustment of vertical valid line timing signal VVALT [7:4]
Register Setting Value (Ox)
:Adjusting the starting position
8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Line)
VVALT [3:0]
Register Setting Value (Ox)
:Adjusting the end position
8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Line)
AGC Loop filter control AGCLF [5:0]
Register Setting Value (Ox)
:Adjusting sync level
MSB [5 : 4] 3 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31
2 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
38/47
Semiconductor Sync separation level SSEPL [6:0]
Register Setting Value (Ox)
MSM7662
:Adjusting the blanking level
MSB [6 : 4] 4 5 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 6 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 7 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 3 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
-64 -63 -62 -61 -60 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49
ACC Loop filter control ACCLF [4:0]
Register Setting Value (Ox)
:Adjusting the color burst level
MSB [4] 1 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
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Semiconductor Hue control Adjustment of color subcarrier phase HUE [7:0]
Register Setting Value (Ox)
MSM7662
MSB [7 : 4] 8 9 A B C
-90.0 -88.6 -87.2 -85.8 -84.4 -83.0 -81.6 -80.2 -78.8 -77.3 -75.9 -74.5 -73.1 -71.7 -70.3 -68.9
D
-67.5 -66.1 -64.7 -63.3 -61.9 -60.5 -59.1 -57.7 -56.3 -54.8 -53.4 -52.0 -50.6 -49.2 -47.8 -46.4
E
-45.0 -43.6 -42.2 -40.8 -39.4 -38.0 -36.6 -35.2 -33.8 -32.3 -30.9 -29.5 -28.1 -26.7 -25.3 -23.9
F
-22.5 -21.1 -19.7 -18.3 -16.9 -15.5 -14.1 -12.7 -11.3 -9.8 -8.4 -7.0 -5.6 -4.2 -2.8 -1.4
0
+0.0 +1.4 +2.8 +4.2 +5.6 +7.0 +8.4 +9.8 +11.3 +12.7 +14.1 +15.5 +16.9 +18.3 +19.7 +21.1
1
+22.5 +23.9 +25.3 +26.7 +28.1 +29.5 +30.9 +32.3 +33.8 +35.2 +36.6 +38.0 +39.4 +40.8 +42.2 +43.6
2
+45.0 +46.4 +47.8 +49.2 +50.6 +52.0 +53.4 +54.8 +56.3 +57.7 +59.1 +60.5 +61.9 +63.3 +64.7 +66.1
3
+67.5 +68.9 +70.3 +71.7 +73.1 +74.5 +75.9 +77.3 +78.8 +80.2 +81.6 +83.0 +84.4 +85.8 +87.2 +88.6
4
+90.0 +91.4 +92.8 +94.2 +95.6 +97.0 +98.4 +99.8
5
6
7
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
-180.0 -157.5 -135.0 -112.5 -178.6 -156.1 -133.6 -111.1 -177.2 -154.7 -132.2 -109.7 -175.8 -153.3 -130.8 -108.3 -174.4 -151.9 -129.4 -106.9 -173.0 -150.5 -128.0 -105.5 -171.6 -149.1 -126.6 -104.1 -170.2 -147.7 -125.2 -102.7 -168.8 -146.3 -123.8 -101.3 -167.3 -144.8 -122.3 -165.9 -143.4 -120.9 -164.5 -142.0 -119.5 -163.1 -140.6 -118.1 -161.7. -139.2 -116.7 -160.3 -137.8 -115.3 -158.9 -136.4 -113.9 -99.8 -98.4 -97.0 -95.6 -94.2 -92.8 -91.4
+112.5 +135.0 +157.5 +113.9 +136.4 +158.9 +115.3 +137.8 +160.3 +116.7 +139.2 +161.7 +118.1 +140.6 +163.1 +119.5 +142.0 +164.5 +120.9 +143.4 +165.9 +122.3 +144.8 +167.3
+101.3 +123.8 +146.3 +168.8 +102.7 +125.2 +147.7 +170.2 +104.1 +126.6 +149.1 +171.6 +105.5 +128.0 +150.5 +173.0 +106.9 +129.4 +151.9 +174.4 +108.3 +130.8 +153.3 +175.8 +109.7 +132.2 +154.7 +177.2 +111.1 +133.6 +156.1 +178.6
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Semiconductor
MSM7662
Filter Characteristics
Band Pass Filter (NTSC ITU-R601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
Band Pass Filter (PAL ITU-R601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
41/47
Semiconductor
MSM7662
Trap Filter (NTSC ITU-R601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
Trap Filter (PAL ITU-R601)
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
42/47
Semiconductor
MSM7662
Pre Filter
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
Sharp Filter
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 Frequency [MHz]
43/47
Semiconductor
MSM7662
Decimation Filter
0
-20
Level [dB]
-40
-60
-80
-100 0 2 4 6 8 10 12 Frequency [MHz]
44/47
Semiconductor
MSM7662
BASIC APPLICATION CIRCUIT EXAMPLES
1) Application Circuit for FIFO-1 and FIFO-2 Modes
3.3 V or 5 V 4.7 kW Video in (Composite Y input) 1 mF 75 W 4 I2C Controller 4.7 kW 1000 pF 1000 pF 1000 pF 47 mF 47 mF 47 mF
10 mF 10 mF
SDA SCL RESET_L AVDD VIN(1:4) VRT1 AMPOUT ADIN1 CLPOUT1 VRCL1 1 mF VRB1 MSM7662
DAVDD
DVDD Y(7:0) C(7:0) B(7:0) Video LSI
10 kW Video in (C input) 75 W
1 mF 2
10 mF
10 mF
VIN(5:6) VRT2 AMPOUT2 ADIN2 1 mF CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
HVALID VVALID ODD HSYNC_L VSYNC_L CLKX2O CLKXO CLKX2 OSC
* Connect the M7662 decoder and a video LSI device according to the output interface (ITUR656, 8-bit [YCbCr], 16-bit [YCbCr], RGB). * Video input can be five composite inputs or two S-Video inputs. * Connect unused video input pins to AGND. If a composite signal is input, the C input side (video amp, A/D converter, etc.) will be in the OFF operation state. * If the input is limited by the composite signal, connect VIN (5:6), VRT2, VRB2, AMPOUT2, ADIN2, and CLPOUT2 pins to AGND. Externally attached components such as capacitors may be removed. * Set the MODE[3:0] pins to the prescribed setting. * Supply power and GND for analog, A/D, and digital circuits on the circuit board should be separated at the power source wherever possible. Power and GND lines for analog and A/D circuits must be wide and low impedance.
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Semiconductor 2) Application Circuit for FM-1 and FM-2 Modes
MSM7662
3.3 V or 5 V 4.7 kW Video in (Composite Y input) 1 mF 75 W I2C Controller 4.7 kW
1000 pF 1000 pF 1000 pF 47 mF 47 mF 47 mF Memory control signal
10 mF 10 mF
SDA SCL RESET_L AVDD VIN(1:4) VRT1 AMPOUT ADIN1 CLPOUT1 VRCL1 1 mF VRB1
DAVDD
DVDD
M[7:4] Y(7:0) C(7:0) B(7:0)
Field memory Field memory Video LSI
10 kW Video in (C input) 1 mF 75 W 10 mF
MSM7662
10 mF
VIN(5:6) VRT2 AMPOUT2 ADIN2 1 mF CLPOUT2 VRB2 AGND DAGND DGND MODE[3:0]
CLKXO HVALID VVALID ODD HSYNC_L VSYNC_L CLKX2O CLKX2 OSC
* Select either 16-bit [YCbCr] or RGB output as the output interface. * Number of field memories utilized 16-bit [YCbCr]: Use 2 field memories. RGB: Use 3 field memories. * Video input can be five composite inputs or two S-Video inputs. * Connect unused video input pins to AGND. If a composite signal is input, the C input side (video amp, A/D converter, etc.) will be in the OFF operation state. * If the input is limited by the composite signal, connect VIN (5:6), VRT2, VRB2, AMPOUT2, ADIN2, and CLPOUT2 pins to AGND. Externally attached components such as capacitors may be removed. * Set the MODE[3:0] pins to the prescribed setting. * For the MF-1 mode setting, externally generate and supply control signals for the field memory. * For the MF-2 mode setting, memory control signals from M[7:4] can be supplied to the field memory. * For the MF-2 mode setting, the output timing for HSYNC_L, VSYNC_L, ODD, VVALID, and HVALID becomes the memory read timing. Data output from memory is aligned with the variout sync signal timings. (See page 24 and page 25) * Supply power and GND for analog, A/D, and digital circuits on the circuit board should be separated at the power source wherever possible. Power and GND lines for analog and A/D circuits must be wide and low impedance. 46/47
Semiconductor
MSM7662
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-28-41
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan

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